1. Field of the Invention
The present invention relates to a twisted bit-line architecture of a semiconductor memory having block select transistors, and is used for, in particular, a T (transistor) C (capacitor) unit type ferroelectric RAM (FeRAM).
2. Description of the Related Art
In a memory product having a memory cell array composed of a plurality of memory cells disposed in a matrix form, wiring intervals such as intervals of bit-lines or intervals of word lines have been being made extremely narrower in accordance with the miniaturization of memory cells.
As a result, in particular, in a memory for reading a minute signal from a memory cell such as a dynamic random access memory (DRAM) or a ferroelectric memory (FeRAM) to a bit-line, there is a significant effect on the minute signal under interference (noise) among bit-lines, which causes a malfunction.
Then, in order to absorb interference between adjacent bit-lines, a twisted bit-line architecture in which these bit-lines are elongated in one direction while being twisted is used in such a memory product (for example, refer to H. Hidaka et al, “Twisted bit-line architectures for Multi-Megabit DRAM's” IEEE J. Solid-State Circuits, vol. 24, No 1, pp. 21-27, February 1989).
In a case of using a twisted bit-line architecture, however, it is necessary to newly provide regions for twisting adjacent bit-lines in a memory cell array.
Therefore, by taking a dynamic random access memory as an example, a region A for twisting directly results in an increase of an area of a memory cell array as shown in FIG. 18.
Accordingly, also in a case of using a twisted bit-line architecture in a semiconductor memory having block select transistors, i.e., in a TC unit type FeRAM, it is necessary to solve the problem of an increase of a memory cell array.